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Samsung touts 96% lower-power NAND design — researchers investigate design based on ferroelectric transistors

Samsung researchers have published a detailed account of an experimental NAND architecture that aims to cut one of the technology’s largest power drains by as much as 96%. The work — Ferroelectric ...
Nanowerk

Vacuum channel transistor suppresses gate leakage to enter chip circuits

A vacuum channel transistor controls electrons at the cathode to suppress gate leakage, letting it work inside amplifiers and NAND and NOR logic gates. (Nanowerk News) A research team in China has ...
Nanowerk

Printed organic transistors achieve record performance and 3D circuit density

(Nanowerk Spotlight) Organic semiconductors have long held promise for enabling deformable electronic devices that can be manufactured at low cost and high volumes using printing techniques. However, ...
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Samsung Electronics debuts 3D stacked logic transistors, wins VLSI best paper

Samsung Electronics has implemented three-dimensional (3D) stacked transistor technology to overcome the miniaturization limits of logic semiconductors. By applying the concept of vertical stacking ...